1. Field of the Invention
The present invention relates to a mixing circuit, and, more particularly, to a still-picture signal/motion-picture signal mixing circuit in a color signal processor or a luminance signal processor.
2. Description of the Prior Art
FIG. 1 shows a conventional mixing circuit for MUSE(multiple sub-nyquist sampling encoding) in a color signal processor. As shown in FIG. 1, the conventional mixing circuit has a still-picture signal input terminal 51, a 1-bit right shifter 52, a 2-bit right shifter 53, an adder 54, a 1-bit right shifter 55, a 2-bit right shifter 56, a multiplexer 57, a motion-picture signal input terminal 58, a 1-bit right shifter 59, a 2-bit right shifter 60, an adder 61, a 1-bit right shifter 62, a 2-bit right shifter 63, a multiplexer 64, an adder 65, and an output terminal 66.
The function of this mixing circuit will now be described. A still-picture signal (S) input from the still-picture signal input terminal 51 is divided to S/2 by the 1-bit right shifter 55, to S/4 by the 2-bit right shifter 56, and to 3S/4 by the 1-bit right shifter 52, 2-bit right shifter 53 and adder 54. The multiplexer 57 selects one of those signals S, S/2, S/4 and 3S/4 in accordance with shift signals CI2 to CI0.
A motion-picture signal (M) input from the motion-picture signal input terminal 58 is divided to M/2 by the 1-bit right shifter 62, to M/4 by the 2-bit right shifter 63, and to 3M/4 by the 1-bit right shifter 59, 2-bit right shifter 60 and adder 61. The multiplexer 64 selects one of those signals M, M/2, M/4 and 3M/4 in accordance with shift signals CI2 to CI0.
The still-picture signal and motion-picture signal respectively selected by the multiplexers 57 and 64 are added together by the adder 65, and the resultant signal is output from the output terminal 66. The outputs of the multiplexers 57, 64 and the adder 65 in accordance with each combination of the shift signals CI2-CI0 are given in Table 1. This Table 1 shows the relationship between the input patterns of the shift signals CI2-CI0 and those outputs in FIG. 1.
A conventional mixing circuit for MUSE in a luminance signal processor, as shown in FIG. 2, has a still-picture signal input terminal 71, a motion-picture signal input terminal 72, a subtracter 73, a 1-bit right shifter 74, a 2-bit right shifter 75, a 3-bit right shifter 76, a 4-bit right shifter 77, AND gates 78, 79, 80 and 81, adders 82 and 83, a switch 84, adders 85 and 86, a shift-signal input terminal 87 and an output terminal 88.
The function of this mixing circuit will be described below. A still-picture signal (S) input from the still-picture signal input terminal 71 is subtracted from a motion-picture signal (M) input from the motion-picture signal input terminal 72 by the subtracter 73. The output (M-S) of this subtracter 73 is converted to (M-S)/2 by the 1-bit right shifter 74, (M-S)/4 by the 2-bit right shifter 75, (M-S)/8 by the 3-bit right shifter 76, and (M-S)/16 by the 4-bit right shifter 77. The outputs of those shifters 74 to 77 are allowed to pass the respective AND gates 78 to 81 in accordance with the combination of shift signals KI3KI0 input from the shift-signal input terminal 87. The outputs of those AND gates 78 to 81 are put through the associated adders 82, 83, 85 and 86, and the resultant signal is output from the output terminal 88. It is to be noted that when the shift signals KI3-KI0 are all "1", the switch 84 selects the other input that the one coming from the adder 82 (and selects the input from the adder 82 otherwise), and the outputs of the AND gates 78 to 81 are all "0."
The outputs of the subtracter 73 and the adders 82, 83, 85 and 86 in accordance with each combination of the shift signals KI3-KI0 are given in Table 2. This Table 2 shows the relationship between the input patterns of the shift signals KI3-KI0 and those outputs in FIG. 2.
The conventional mixing circuits for MUSE disadvantageously contain many adders which have a large circuit size.
TABLE 1 ______________________________________ OUTPUT OF OUTPUT OF OUTPUT CI CI CI MULTIPLEXER MULTIPLEXER OF 2 1 0 57 64 ADDER 65 ______________________________________ 0 0 0 S 0 S 0 0 1 3S/4 M/4 3S/4 + M/4 0 1 0 S/2 M/2 S/2 + M/2 0 1 1 S/4 3M/4 S/4 + 3M/4 1 0 0 0 M M ______________________________________
TABLE 2 __________________________________________________________________________ OUTPUT OF OUTPUT OF OUTPUT OF OUTPUT OF OUTPUT OF KI 3 KI 2 KI 1 KI 0 SUBTRACTER 73 ADDER 82 ADDER 83 ADDER 85 ADDER 86 __________________________________________________________________________ 0 0 0 0 M - S 0 0 0 S 0 0 0 1 M - S 0 (M - S)/16 (M - S)/16 15S/16 + M/16 0 0 1 0 M - S 0 (M - S)/8 2(M - S)/16 14S/16 + 2M/16 0 0 1 1 M - S 0 3(M - S)/16 3(M - S)/16 13S/16 + 3M/16 0 1 0 0 M - S (M - S)/4 0 4(M - S)/16 12S/16 + 4M/16 0 1 0 1 M - S (M - S)/4 (M - S)/16 5(M - S)/16 11S/16 + 5M/16 0 1 1 0 M - S (M - S)/4 (M - S)/8 6(M - S)/16 10S/16 + 6M/16 0 1 1 1 M - S (M - S)/4 3(M - S)/16 7(M - S)/16 9S/16 + 7M/16 1 0 0 0 M - S (M - S)/2 (M - S)/16 9(M - S)/16 7S/16 + 9M/16 1 0 0 1 M - S (M - S)/2 (M - S)/8 10(M - S)/16 6S/16 + 10M/16 1 0 1 0 M - S (M - S)/2 3(M - S)/16 11(M - S)/16 5S/16 + 11M/16 1 0 1 1 M - S 3(M - S)/4 0 12(M - S)/16 4S/16 + 12M/16 1 1 0 0 M - S 3(M - S)/4 (M - S)/16 13(M - S)/16 3S/16 + 13M/16 1 1 0 1 M - S 3(M - S)/4 (M - S)/8 14(M - S)/16 2S/16 + 14M/16 1 1 1 0 M - S 3(M - S)/4 3(M - S)/16 15(M - S)/16 S/16 + 15M/16 1 1 1 1 M - S 0 0 M - S M __________________________________________________________________________